東勢厝yang 雜七雜八亂亂記

資料：

cd4538_datasheet

cd4538_簡中資料

使用CPLD 模擬cd4538 

bsf

cd4538a VHDL

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY cd4538a IS

PORT
(
clk1 : IN STD_LOGIC;
sinin : IN STD_LOGIC;
limcnt : IN STD_LOGIC_VECTOR(7 downto 0);
sinout : OUT STD_LOGIC
);

END cd4538a;

ARCHITECTURE cd4538a_architecture OF cd4538a IS

signal cnt:std_logic_vector(7 downto 0);
signal cnt1:std_logic_vector(7 downto 0);
SIGNAL outstat : STD_LOGIC;

BEGIN
sinout <= outstat ;

sinup:process (sinin,clk1)
begin

if rising_edge(clk1) then
   if sinin = '0' then
      cnt <= limcnt ;
      if cnt1 = 0 then
           outstat <= '0';
      else
           cnt1 <= cnt1 - 1;
           outstat <= '1';
      end if;
   else
      cnt1 <= limcnt;
      if cnt = 0 then
           outstat <= '0';
      else
           cnt <= cnt - 1;
           outstat <= '1';
      end if;
   end if;
end if;

end process sinup;

END cd4538a_architecture;

CLK_10000us VHDL

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY clk_10000us IS

PORT
(
reset : IN STD_LOGIC;
clkin : IN STD_LOGIC;
clkout100 : OUT STD_LOGIC
);


END clk_10000us;

ARCHITECTURE clk_10000us_architecture OF clk_10000us IS

signal cnt: STD_LOGIC_VECTOR(4 downto 0);
signal outstat100 : STD_LOGIC;
signal cnt100us : std_logic_vector(15 downto 0);
signal stat100us:std_logic;
BEGIN
clkout100 <= outstat100 ;

sinup:process (clkin)

begin

if clkin = '1' then
cnt <= cnt + 1;
if cnt = 31 then
cnt100us <= cnt100us + 1 ;
if cnt100us >= 10000 then
cnt100us <= "0000000000000000";
end if;
end if;
end if;
if cnt100us >= 0 and cnt100us <= 49 then stat100us <= '1' ; else stat100us <= '0' ; end if ;
end process sinup;

outstat100<= stat100us;

END clk_10000us_architecture;